Deviations from Moore's Law

The semiconductor industry is facing a challenge, that is, the cycle of micro-chip feature sizes has already ended every two years, and we are entering a highly unknown stage. Several key challenges currently faced by the industry show that the shrinking distance of wafers is becoming increasingly difficult.

1. The foundry's mass production of 32/28 nm wafers has been extended to around three years. In 2009, 45/40nm wafers accounted for only 10% of foundry revenue; in the fourth quarter of 2012, 32/28nm accounted for 10% of foundry revenue.

2. After 22 years of mass production at 32nm, the 22nm FinFET was announced to be mass-produced. FinFET is a very challenging technology. Intel's research in this area is quite outstanding, but still need to overcome many challenges in order to support the multi-threshold voltage and multi-VDD level that the new generation SoC needs.

3. The next-generation 20nm planar CMOS will face more tolerance control challenges than the 28nm process. This can have a major impact - the cost per gate at 20nm will be higher than 28nm.

Figure: Cost per gate.

Since the cost of each gate is likely to increase, there will actually be more work to be done in the next-generation process, which will extend the design completion time. In addition, the cost per gate for the 14 nm generation may also be higher than 28 nm.

What is the next step after 4.20nm? The semiconductor industry is working to develop 14nm FinFETs. They can indeed be developed, but will face more challenges in manufacturing, including step coverage, FIN size control, double patterning on multiple layers, and even using quadruple graphics.

In addition, EUV technology obviously will not be ready in 2014~2015, so the industry still has to continue to use 193nm tools. The recent inspection of the 28nm production line also showed that many technologies are approaching the limit.

Another key issue is whether the FinFET can achieve multi-VDD level and multi-threshold voltages on the wafer.

The industry has a lot of work to do. It must develop new component libraries, IP must transition to FinFET architecture, must test the operation of the chip, and also ensure that it can be mass-produced. In the 14nm generation, complex wafers will cost 200-500 million U.S. dollars in design costs, and even if they are reworked, they must spend 20 million to 50 million U.S. dollars. Not to mention the cost of design failure.

More importantly, until 2016 or 2017, it appears that no company other than Intel will mass-produce 14nm FinFETs. To reach the mass production stage, we must ensure that we can achieve lower power consumption than previous generations of technology, as well as more cost per gate.

After 14nm, there will be new challenges (EUV, 450mm, carbon nanotubes, etc.). The semiconductor industry must understand that the daunting challenges will continue to come and that the time to move to smaller features will continue to increase.

This means that the entire supply chain, including mold suppliers, photomask manufacturers, foundries, IC design companies, and electronics manufacturers must all be adjusted.

From a hardware point of view, the most important adjustment Apple has made this time when it is launching the next-generation iPad is only the higher-resolution display.

For wafer suppliers, if they do not make corresponding adjustments, then the cost of 10,000 wafers per month, up to $1 billion, is amazing.