Not long ago, Huaxing Wanbang analysts saw that some domestic chip design companies are highly innovative in terms of algorithms, but the system-on-chip (SoC) chip that comes back has been used because local temperatures are too high or the design cannot reach the target power consumption. A lot of time to modify the chip layout and re-design the back-end. This extends the time to market, so domestic manufacturers need new tools to optimize the architectural power and thermal performance. For this reason, Huaxing Wanbang has visited DOCEA, an emerging EDA vendor that provides such tools. DOCEA has received a lot of praise from the industry for its innovative technology and has shown great interest in cooperation with Chinese manufacturers. Located in the Grenoble area known as the "Silicon Valley of France," STMicroelectronics has an R&D center with 6,000 employees in the area, as well as a headquarters for marketing, design and industrialization, so the area is nurturing many emerging European countries. Semiconductor companies. DOCEA was established in Grenoble in 2006 under the auspices of Venture Capital and is an EDA tool provider focused on providing architectural power and thermal management.
French “Silicon Valley†among the mountains of Grenoble, France
As the capabilities and applications supported by portable electronics continue to increase, factors such as battery life, heat dissipation in small spaces, and reliability make power management increasingly important. At the same time, the development of semiconductor technology in chip design, front-end manufacturing, and back-end packaging, such as more and more system-on-chip (SoC), system-in-package (SiP) and chip 3D stacking technologies, etc. Thermal management raises higher challenges. In addition, national governments have passed laws and regulations that impose increasingly stringent power consumption (such as Energy Star), making it necessary to implement system energy conservation from the very beginning of chip design.
From the chip design itself, early architecture design is the most critical factor in determining the chip's success and time to market. This basic rule also applies to power consumption and thermal management of chips and systems. According to a survey, of the many factors that affect chip power optimization, more than 70% of respondents believe that chip architecture design is the most important, followed by 20% of respondents who believe that logic synthesis is critical.
"In response to these current power and thermal management requirements and challenges in chip design, we have developed a set of software that can describe and predict the different power and thermal performance of various chip designs from the very beginning. It can help Designers decided on the best chip architecture early on,†said Ghislain Kaiser, co-founder and CEO of DOCEA, to Huaxing Wanbang analysts. “It is a solution that separates the possible 'hazard' that can easily establish a power and thermal ESL model before the chip's functional code is written, and can include both system and software design. Share with the entire design team, including the division."
The ACEplorer and ACE Power Modeler introduced by DOCEA are tools for analyzing and modeling power consumption and thermal behavior at the architecture level. It can fully implement rapid security modeling, decision support estimation, early detection and risk analysis, and various solutions. Program proposal and exploration and other functions. It also supports UPF's low-power design flow, seamlessly integrates with a variety of design environments, and generates power consumption data that can be reported and reused.
DOCEA's core team: Co-founder and Chief Technology Officer Sylvian Kaiser, Co-Founder & CEO Ghislain Kaiser, Sales & Marketing Director Ridha Hamza
The EDA tool separates the various power and thermal behaviors that are intertwined in the chip design, such as the power and thermal behavior of various intellectual property (IP) on the chip, and the thermal performance of various layouts and wirings. The impact of various application scenarios on different units, the effects of various software on thermal performance, and so on. For example, different application loads cause power consumption and heat generation in the processor unit and memory.
By recombining these different power and thermal performance analyses, it is possible to produce relevant dynamic power and thermal behavior simulations, or to propose the best management and optimization options, and to output them in UPF format and provide graphical UPF instructions and generate power consumption profiles at different implementation costs for design decisions. At the same time, the ACE Power Modeler can extract ESL power models from simulations, library files, and test values ​​of existing IPs, and can explore new process nodes.
"ACEplorer is a very good decision support tool that enables chip and system designers to implement low-power optimization, power consumption and application scenario modeling, and power management planning at the beginning of design." DOCEA Director of Sales and Marketing Ridha Hamza said. "The benefits it brings include exploring the maximum design space at the architectural level, which can reduce power consumption by up to 70%; designers can quickly select the most low-power technology (hardware and software) and performance by quickly evaluating the model. Better balance; early thermal performance convergence, avoiding redesign; communicating with your customers on low-power solutions, etc."
ST-Ericsson used this ACEplorer to design a series of platforms for smart phones and ordinary mobile phones, including several chips such as SoC, RF and power management chips. The 45nm CMOS industry uses a total of more than 300 digital and analog IPs, and incorporates multiple power management techniques such as clock gating, power gating, DVFS, multiple Vt banks, and retention memory. Using this technology, the difference between ESL estimates and actual chip power consumption is less than 15%. The ESL model promotes and accelerates software development. The entire SoC and platform team share power consumption data.
At present, the company has established partnerships with companies and organizations such as Synopsys, CoFluent, Magilem and CEA, and established application partnerships with the top 5 chip manufacturers in the world. The products have entered many chip development companies and have been established in the United States and Japan. Distribution support system. The rapid development of China's semiconductor industry has also aroused the company's great attention, and it is anxious to establish cooperative relationships with chip design companies, EDA tool distributors, system integrators and foundries in China in different fields.