All peripherals of the Nios system are connected to the Nios CPU through the Avalon bus. The Avalon bus is a simple protocol on-chip bus. The Nios exchanges data with the outside world through the Avalon bus.

Avalon bus interface classification

Can be divided into two categories: Slave and Master. The slave is a slave interface and the master is a master interface. The main difference between slave and master is the control of the Avalon bus. The master interface has control over the Avalon bus, while the slave interface is passive. Common Avalon transmission structures are: Avalon bus slave read, Avalon bus with a delay state read, Avalon bus slave write, Avalon bus with a delay state from write.

The characteristics of the Avalon bus are

All peripheral interfaces are synchronized to the Avalon bus clock and do not require a complex handshake/response mechanism. This simplifies the timing behavior of the Avalon bus and facilitates the integration of high-speed peripherals. The performance of the Avalon bus and the entire system can be evaluated using standard synchronous timing analysis techniques.

All signals are active high or low, facilitating high-speed signal transmission on the bus. In the Avalon bus, the data selector (rather than the tri-state buffer) determines which signal drives which peripheral. Therefore, the peripheral does not need to set the output to a high-impedance state even when it is not selected.

To facilitate the design of peripherals, address, data, and control signals use separate, dedicated ports. The peripheral does not need to recognize the address bus cycle and the data bus cycle, nor does it need to invalidate the output when it is not selected. Separate address, data, and control channels also simplify the connection to on-chip user-defined logic.

Other features and conventions

The Avalon bus also includes many other features and conventions to support the SOPC Builder software to automatically generate systems, buses and peripherals, including:

Up to 4GB of address space - memory and peripherals can be mapped anywhere in the 32-bit address space

Built-in address decoding - The Avalon bus automatically generates chip select signals for all peripherals, greatly simplifying the design of peripherals based on the Avalon bus

Multi-master bus architecture - Multiple master peripherals can be included on the Avalon bus and arbitration logic is automatically generated

Wizards help users configure the system - SOPC Builder provides graphical wizards to help users with bus configuration (adding peripherals, specifying master/slave relationships, defining address images, etc.). The Avalon bus structure will be automatically generated based on the parameters entered by the user in the wizard.

Dynamic Address Alignment - If the bus widths of the two parties participating in the transfer are inconsistent, the Avalon bus automatically handles the details of the data transfer, allowing peripherals of different data bus widths to be easily connected

Avalon bus module provides services for peripherals

The Avalon bus module provides the following services for Avalon peripherals connected to the bus:

Data Channel Multiplexing - The multiplexer of the Avalon bus module transfers data from the selected slave peripheral to the associated master peripheral.

Address Decoding - The address decode logic provides a chip select signal for each peripheral. In this way, individual peripherals do not need to decode the address lines to generate chip select signals, simplifying the design of the peripherals.

Wait-State - The generation of a wait state extends the bus transfer for one or more cycles, which is beneficial to meet the needs of some special synchronous peripherals. When the slave peripheral cannot respond within one clock cycle, the resulting wait state can cause the master peripheral to enter a wait state. A wait state can also be generated when the read enable and write enable signals require a certain settling time/hold time requirement.

Dynamic Bus Width - Dynamic bus width hides the details of narrow-bandwidth peripherals interfaced with the wider Avalon bus (or Avalon bus with higher bandwidth peripherals). For example, when a 32-bit master reads data from a 16-bit memory, the dynamic bus width automatically reads the 16-bit memory twice to transfer 32-bit data. This reduces the complexity of the logic and software of the master device because the master device does not need to care about the physical characteristics of the peripheral device.

Interrupt-Priority Allocation - When one or more slave peripherals generate an interrupt, the Avalon bus module determines the interrupt request based on the corresponding interrupt request number (IRQ).

Latent Transfer capability - Logic with delayed transfer between master and slave devices is included inside the Avalon bus module.

Streaming Read and Write Capabilities—The logic that enables streaming between master and slave devices is contained within the Avalon bus module.

Overview of Avalon bus based on Nios system

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