Being able to distinguish between signals and noise is a key aspect of many signal acquisition systems. Whether it's a clear telecommunications protocol, radar scanning, or measuring instruments, collecting weak signals and interpreting them is central to distinguishing the performance of any system. For GSPS ADCs, one of the most important AC performance parameters might be SFDR. In simple terms, this parameter specifies the ability of the ADC and the system to interpret the carrier signal from other noise or any other spurious frequencies.
This is a FFT of a single-chip 12-bit ADC, where the third harmonic is the main contributor to SFDR. In this case, the dynamic range from the fundamental (–1 dBFS) to the third harmonic (–82 dBFS) is –81 dBc because the dynamic range is relative to the carrier power.
figure 1
Eliminate interlaced artifacts using GSPS ADC
GSPS ADCs with high-bandwidth SFDRs are currently available, and such devices do not have interlaced artifacts that have previously limited system performance. The AD9860 is a dual, 14-bit, 1 GSPS ADC that achieves SFDR of 78 dBc at 1 GHz input. The AD9625 is a 12-bit, 2 GSPS ADC that achieves a typical wideband SFDR of 80 dBc at 1 GHz input.
SFDR is an important and key performance indicator for GSPS and ADC. Wideband SFDR is generally limited by the second or third harmonic of the fundamental signal. Single-channel, single-chip pipelined ADCs and other advanced architectures have opened up a new frontier for high-performance GSPS converters. In the frequency domain, they do not have the staggered spurs that the ADC architecture has shown in the GSPS space.
Viewing, planning, and removing these artifacts can be problematic for applications that require broadband response. New solutions address these system issues while providing the most advanced SFDR performance across the wideband spectrum.
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